33 research outputs found

    Design of reconfigurable embedded systems using Software-defined on-Chip interconnect elements

    Get PDF
    El conjunto de aplicaciones que hoy en día se ejecutan en los elementos de procesamiento en el interior de un Sistema en Chip (System-on-Chip (SoC), en inglés) requieren que el sistema de interconexión que los conecta, les permita cumplir con los requerimientos de Calidad en el Servicio (Quality of Service (QoS), en inglés) que les fueron establecidos. Los actuales sistemas de interconexión deben ser flexibles, reconfigurables, escalables, reutilizables y fáciles de administrar. En este documento se presenta una solución para un sistema de interconexión tipo bus basado en el paradigma de Redes Definidas por Software (Software Defined Network (SDN), en inglés). El trabajo muestra la arquitectura general del sistema de interconexión y en él se demuestra que la arquitectura cumple con las características anteriormente mencionadas. El trabajo pone especial énfasis en la capa de infraestructura del sistema -hardware-. Además, se incluyen los elementos de la capa de sistema operativo de red y se establecen sus interrelaciones con las capas adyacentes. En este trabajo también se muestra una nueva política de arbitraje basada en presupuestos la cual permite el uso diferenciado del bus. La política muestra un mejor comportamiento cuando el sistema funciona en escenarios ejecutando aplicaciones con tareas dependientes, los cuales son muy comunes en la actualidad. El sistema fue modelado en SystemC con precisión de ciclo de reloj. Las contribuciones realizadas en este trabajo pueden ser extrapoladas a otros sistemas de interconexión en SoC debido a que los retos que comparten son similares.The set of applications that today run in the processing elements inside a Systemon- Chip (SoC) require that the SoC interconnection system allows them to meet the Quality of Service (QoS) requirements that were established. Current interconnection systems must be exible, recon_gurable, scalable, reusable and easy to manage. This document presents a solution for a bus type interconnection system, based on the Software De_ned Network (SDN) paradigm. The work shows the general architecture of the interconnection system and demonstrates that this architecture meets the characteristics mentioned above. The work puts special emphasis on the infrastructure layer of the system | hardware |. However, it also establishes the elements to be included in the network operating system layer and its interrelation with the adjacent layers. This work also shows a new arbitration policy based on budgets that allows the di_erentiated use of the bus.The policy presents the best behavior when the system works in scenarios with applications executing dependent tasks, which are very common nowadays. The system was modeled in SystemC with clock cycle accuracy. The contributions made in this work can be extrapolated to other SoC interconnection systems because the challenges they share are similar

    DISEÑO DE UN IP CORE PARA UNA INTERFAZ SPI (DESIGN OF AN IP CORE FOR A SPI INTERFACE)

    Get PDF
    Resumen Este trabajo presenta el desarrollo de un IP CORE (Intellectual Property Core, núcleo de propiedad intelectual) con la funcionalidad de una interfaz SPI (Serial Peripheral Interface, interfaz periférica serial) de alta velocidad y con diferentes frecuencias de operación, cuyo objetivo es establecer comunicación (transmisión/recepción de datos) entre la tarjeta de desarrollo Zedboard a otros dispositivos. El IP CORE de la interfaz SPI está diseñado en base a una simple metodología, donde tiene por elementos principales un registro de desplazamiento PISO (Parallel Input Serial Output, entrada paralela salida serial) para la transmisión y un registro SIPO (Serial Input Parallel Output, entrada serial salida paralela) para la recepción de datos. Dicho módulo fue diseñado y verificado en el software Vivado, con el diseño de bancos de prueba (test bench), donde se obtuvieron resultados aceptables que prueban la funcionalidad y confiabilidad del módulo. Palabras Clave: Diseño, IP CORE, sistema embebido, SPI. Abstract This work presents the development of an IP CORE (Intellectual Property Core) with the funcionality of a high speed interface Serial Peripheral Interface (SPI) with diferent operating frequencies, whose objective is to establish communication (data transmission / reception) between the Zedboard development card to other devices. The IP CORE of the SPI interface is designed based on a simple methodology, where its main elements are a PISO (Parallel Input Serial Output) shift register for transmission and SIPO (Serial Input Parallel Output) register for data reception. Said module was designed and verified in the Vivado software, with the design of test bench, where aceptable results were obtained that prove the functionality and reliability of the module. Keywords: Design, IP CORE, embedded system, SPI

    Low-textured regions detection for improving stereoscopy algorithms

    Get PDF
    The main goal of stereoscopy algorithms is the calculation of the disparity map between two frames corresponding to the same scene, and captured simultaneously by two different cameras. The different position (disparity) where common scene points are projected in both camera sensors can be used to calculate the depth of the scene point. Many algorithms calculate the disparity of corresponding points in both frames relying on the existence of similar textured areas around the pixels to be analyzed. Unfortunately, real images present large areas with low texture, which hinder the calculation of the disparity map. In this paper we present a method that employs a set of local textures to build a classifier that is able to select reliable pixels where the disparity can be accurately calculated, improving the precision of the scene map obtained by the stereoscopic technique.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. Ministry of Education and Science of Spain under contract TIN2010-16144 and Junta de Andalucía under contract TIC-1692

    A Bandwidth Control Arbitration for SoC Interconnections Performing Applications With Task Dependencies

    Get PDF
    Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. Some strategies proposed in the literature to cope with these issues are Round-Robin, Weighted Round-Robin, Lottery, Time Division Access Multiplexing (TDMA), and combinations. However, a fine-grained bandwidth control arbitration policy is missing from the literature. We propose an innovative arbitration policy based on opportunistic access and a supervised utilization of the bus in terms of transmitted flits (transmission units) that settle the access and fine-grained control. In our proposal, every competing element has a budget. Opportunistic access grants the bus to request even if the component has spent all its flits. Supervised debt accounts a record for every transmitted flit when it has no flits to spend. Our proposal applies to interconnection systems such as buses, switches, and routers. The presented approach achieves deadlock-free behavior even with task dependency applications in the scenarios analyzed through cycle-accurate simulation models. The synergy between opportunistic and supervised debt techniques outperforms Lottery, TDMA, and Weighted Round-Robin in terms of bandwidth control in the experimental studies performed

    A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

    Get PDF
    Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.Las plataformas informáticas actuales fomentan la integración de miles de núcleos de procesamiento y sus interconexiones, en un solo chip. Los smartphones móviles, el IoT, los dispositivos embebidos, los ordenadores de sobremesa y los centros de datos utilizan sistemas en chip (SoC) de muchos núcleos para explotar su potencia de cálculo y paralelismo para satisfacer los requisitos de las cargas de trabajo dinámicas. Las redes en chip (NoC) conducen a una conectividad escalable para diversas aplicaciones con distintos patrones de tráfico y dependencias de datos. Sin embargo, cuando el sistema ejecuta varias aplicaciones en las NoC tradicionales -optimizadas y fijadas en el momento de síntesis, la disconformidad de la interconexión con los requisitos de las distintas aplicaciones genera limitaciones en el rendimiento. En la literatura, los diseños de NoC adoptaron la estrategia de redes definidas por software (SDN) para evolucionar hacia una solución de interconexión adaptable para los futuros chips. Sin embargo, los trabajos estudiados implementan un enfoque parcial de red definida por software en el chip (SDNoC) de SDN, dejando de lado la arquitectura en capas de SDN que aporta interoperabilidad en la red convencional. Este artículo explora la literatura sobre SDNoC y la clasifica en función de las características SDN que presenta cada trabajo. A continuación, describimos los retos y oportunidades detectados a partir del estudio de la literatura. Además, explicamos la motivación para un enfoque SDNoC, y exponemos los conceptos y arquitecturas de SDN y SDNoC. Observamos que los trabajos en la literatura emplean un enfoque SDNoC por capas no completo. Este hecho crea varias áreas fértiles en la arquitectura SDNoC en las que los investigadores pueden contribuir a los diseños de SoCs de muchos núcleos

    Sloan Digital Sky Survey IV: mapping the Milky Way, nearby galaxies, and the distant universe

    Get PDF
    We describe the Sloan Digital Sky Survey IV (SDSS-IV), a project encompassing three major spectroscopic programs. The Apache Point Observatory Galactic Evolution Experiment 2 (APOGEE-2) is observing hundreds of thousands of Milky Way stars at high resolution and high signal-to-noise ratios in the near-infrared. The Mapping Nearby Galaxies at Apache Point Observatory (MaNGA) survey is obtaining spatially resolved spectroscopy for thousands of nearby galaxies (median ). The extended Baryon Oscillation Spectroscopic Survey (eBOSS) is mapping the galaxy, quasar, and neutral gas distributions between and 3.5 to constrain cosmology using baryon acoustic oscillations, redshift space distortions, and the shape of the power spectrum. Within eBOSS, we are conducting two major subprograms: the SPectroscopic IDentification of eROSITA Sources (SPIDERS), investigating X-ray AGNs and galaxies in X-ray clusters, and the Time Domain Spectroscopic Survey (TDSS), obtaining spectra of variable sources. All programs use the 2.5 m Sloan Foundation Telescope at the Apache Point Observatory; observations there began in Summer 2014. APOGEE-2 also operates a second near-infrared spectrograph at the 2.5 m du Pont Telescope at Las Campanas Observatory, with observations beginning in early 2017. Observations at both facilities are scheduled to continue through 2020. In keeping with previous SDSS policy, SDSS-IV provides regularly scheduled public data releases; the first one, Data Release 13, was made available in 2016 July

    Treatment with tocilizumab or corticosteroids for COVID-19 patients with hyperinflammatory state: a multicentre cohort study (SAM-COVID-19)

    Get PDF
    Objectives: The objective of this study was to estimate the association between tocilizumab or corticosteroids and the risk of intubation or death in patients with coronavirus disease 19 (COVID-19) with a hyperinflammatory state according to clinical and laboratory parameters. Methods: A cohort study was performed in 60 Spanish hospitals including 778 patients with COVID-19 and clinical and laboratory data indicative of a hyperinflammatory state. Treatment was mainly with tocilizumab, an intermediate-high dose of corticosteroids (IHDC), a pulse dose of corticosteroids (PDC), combination therapy, or no treatment. Primary outcome was intubation or death; follow-up was 21 days. Propensity score-adjusted estimations using Cox regression (logistic regression if needed) were calculated. Propensity scores were used as confounders, matching variables and for the inverse probability of treatment weights (IPTWs). Results: In all, 88, 117, 78 and 151 patients treated with tocilizumab, IHDC, PDC, and combination therapy, respectively, were compared with 344 untreated patients. The primary endpoint occurred in 10 (11.4%), 27 (23.1%), 12 (15.4%), 40 (25.6%) and 69 (21.1%), respectively. The IPTW-based hazard ratios (odds ratio for combination therapy) for the primary endpoint were 0.32 (95%CI 0.22-0.47; p < 0.001) for tocilizumab, 0.82 (0.71-1.30; p 0.82) for IHDC, 0.61 (0.43-0.86; p 0.006) for PDC, and 1.17 (0.86-1.58; p 0.30) for combination therapy. Other applications of the propensity score provided similar results, but were not significant for PDC. Tocilizumab was also associated with lower hazard of death alone in IPTW analysis (0.07; 0.02-0.17; p < 0.001). Conclusions: Tocilizumab might be useful in COVID-19 patients with a hyperinflammatory state and should be prioritized for randomized trials in this situatio

    Sloan Digital Sky Survey IV: Mapping the Milky Way, Nearby Galaxies, and the Distant Universe

    Get PDF
    We describe the Sloan Digital Sky Survey IV (SDSS-IV), a project encompassing three major spectroscopic programs. The Apache Point Observatory Galactic Evolution Experiment 2 (APOGEE-2) is observing hundreds of thousands of Milky Way stars at high resolution and high signal-to-noise ratios in the near-infrared. The Mapping Nearby Galaxies at Apache Point Observatory (MaNGA) survey is obtaining spatially resolved spectroscopy for thousands of nearby galaxies (median z0.03z\sim 0.03). The extended Baryon Oscillation Spectroscopic Survey (eBOSS) is mapping the galaxy, quasar, and neutral gas distributions between z0.6z\sim 0.6 and 3.5 to constrain cosmology using baryon acoustic oscillations, redshift space distortions, and the shape of the power spectrum. Within eBOSS, we are conducting two major subprograms: the SPectroscopic IDentification of eROSITA Sources (SPIDERS), investigating X-ray AGNs and galaxies in X-ray clusters, and the Time Domain Spectroscopic Survey (TDSS), obtaining spectra of variable sources. All programs use the 2.5 m Sloan Foundation Telescope at the Apache Point Observatory; observations there began in Summer 2014. APOGEE-2 also operates a second near-infrared spectrograph at the 2.5 m du Pont Telescope at Las Campanas Observatory, with observations beginning in early 2017. Observations at both facilities are scheduled to continue through 2020. In keeping with previous SDSS policy, SDSS-IV provides regularly scheduled public data releases; the first one, Data Release 13, was made available in 2016 July

    Sloan Digital Sky Survey IV : mapping the Milky Way, nearby galaxies, and the distant universe

    Get PDF
    We describe the Sloan Digital Sky Survey IV (SDSS-IV), a project encompassing three major spectroscopic programs. The Apache Point Observatory Galactic Evolution Experiment 2 (APOGEE-2) is observing hundreds of thousands of Milky Way stars at high resolution and high signal-to-noise ratios in the near-infrared. The Mapping Nearby Galaxies at Apache Point Observatory (MaNGA) survey is obtaining spatially resolved spectroscopy for thousands of nearby galaxies (median z ~ 0.03). The extended Baryon Oscillation Spectroscopic Survey (eBOSS) is mapping the galaxy, quasar, and neutral gas distributions between z ~ 0.6 and 3.5 to constrain cosmology using baryon acoustic oscillations, redshift space distortions, and the shape of the power spectrum. Within eBOSS, we are conducting two major subprograms: the SPectroscopic IDentification of eROSITA Sources (SPIDERS), investigating X-ray AGNs and galaxies in X-ray clusters, and the Time Domain Spectroscopic Survey (TDSS), obtaining spectra of variable sources. All programs use the 2.5 m Sloan Foundation Telescope at the Apache Point Observatory; observations there began in Summer 2014. APOGEE-2 also operates a second near-infrared spectrograph at the 2.5 m du Pont Telescope at Las Campanas Observatory, with observations beginning in early 2017. Observations at both facilities are scheduled to continue through 2020. In keeping with previous SDSS policy, SDSS-IV provides regularly scheduled public data releases; the first one, Data Release 13, was made available in 2016 July
    corecore